Senior Staff Design Verification Engineer
experience. Significant industry experience in silicon design and/or ASIC verification. Strong proficiency with HDLs: Verilog... and/or VHDL. Strong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera). Solid understanding of digital design...
ASIC & FPGA Design Engineer Senior
, power, cost, and schedule. Build RTL using VHDL/Verilog and drive synthesis, place and route, and timing closure... in Electrical or Computer Engineering, or equivalent practical experience. Demonstrated FPGA design expertise, including VHDL...
Lockheed Martin ⚡ ⚡ Thu, 16 Apr 2026 23:17:01 GMT