RTL Design Engineer
: o Basic Logic Design o Microprocessors o Computer Architecture o Digital design and RTL coding o Verilog/SystemVerilog... and/or VHDL o Synthesis tools (Design Compiler, Genus) o Scripting languages (Python, Perl, TCL) Preferred Qualifications...
Senior FPGA/ASIC Design /Verification Engineer (Onsite)
capture, decomposition, and traceability. Develop RTL design code and simulation in VHDL, Verilog, and/or System Verilog... using VHDL, Verilog, or SystemVerilog. Experience with Linux (or Unix), scripting, C/C++, Python, and/or Perl. Experience...
Raytheon Technologies ⚡ $86800 - 165200 per year ⚡ Mon, 27 Apr 2026 07:07:19 GMT