on creating, implementing, and maintaining FPGA designs using Verilog, SystemVerilog, or VHDL for space-based platforms.... Develop FPGA architectures and modules using Verilog, SystemVerilog, or VHDL for space systems and related applications...
on creating, implementing, and maintaining FPGA designs using Verilog, SystemVerilog, or VHDL for space-based platforms.... Develop FPGA architectures and modules using Verilog, SystemVerilog, or VHDL for space systems and related applications...
using Verilog and/or VHDL. Design and validate DDR3/DDR4 memory interfaces operating up to 800 MHz. Implement and debug... in high-speed digital circuit design. FPGA hardware design experience. Proficiency in Verilog and/or VHDL. Experience...
on creating, implementing, and maintaining FPGA designs using Verilog, SystemVerilog, or VHDL for space-based platforms.... Develop FPGA architectures and modules using Verilog, SystemVerilog, or VHDL for space systems and related applications...
VHDL/Verilog where custom or performance-critical logic is required Implement designs in Vivado through the full flow... closure, and hardware bring-up Highly proficient in RTL design with VHDL and/or Verilog/SystemVerilog, including...
-metal or real-time operating system environments. Exposure to Hardware Description Languages (e.g., VHDL or Verilog... circuit design, PCB layout, FPGA logic using VHDL, or embedded firmware development in C/C++. You will work directly...
Must be proficient in Hardware Description Language (VHDL, Verilog), SystemVerilog, C, C++ Must be proficient in simulation, synthesis... Description Language (HDL), simulation, synthesis, and implementation tools such as Verilog, SystemVerilog, Questa, Synplify, Synopsis...
including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP... Verilog DPI-C integration with existing MATLAB and Python numerical models. Lead the development of reusable custom VIP...
CesiumAstro ⚡ $118000 - 142000 per year ⚡ Tue, 01 Sep 2026 05:32:29 GMT
in a laboratory environment. - Proficiency in Verilog, SystemVerilog, or VHDL; experience with Xilinx Vivado or Microchip Libero... / Vitis with new System Verilog / VHDL RTL code and existing/new IP core integration. The role is located in Northridge...
Lead ASIC Design Engineer
field Experience in one or more RTL languages, including VHDL, Verilog, and/or SystemVerilog Experience leading RTL design...
Mitre ⚡ ⚡ Wed, 02 Sep 2026 02:50:05 GMT