Senior Verification Engineer I
in verification and automation. Deep knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog... best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration...
Semiconductor Design Engineer [Teradyne, N. Reading, MA]
in Verilog and a scripting language (Python, TCL, PERL…) required. Familiarity with System Verilog, UVM, VHDL, C, C++ preferred...
Teradyne ⚡ $140500 per year ⚡ Sat, 28 Mar 2026 08:46:49 GMT