Principal FPGA/ASIC Verification Engineer (Onsite)- Active Secret
designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment. Demonstrated ability to work... tracking Testbench development for the verification of RTL blocks using VHDL or SystemVerilog Recommend new tools...
Principal Applications Engineer
experience. Proficiency in RTL coding using Verilog/VHDL. Experience with high-speed protocols such as Ethernet or PCIe...
Synopsys ⚡ ⚡ Wed, 14 Oct 2026 05:06:57 GMT