technical challenges into actionable solutions. Leveraging your hands-on expertise in Verilog, SystemVerilog, or VHDL... design experience. Proven hands-on expertise in Verilog, SystemVerilog, and/or VHDL for logic design and implementation...
life cycle of high-speed FPGA based digital systems, with experience of leading a design team. Strong proficiency in VHDL.../Verilog with expertise in FPGA design flow using Vivado/Libero EDA tools and familiarity with scripting (TCL/Python/Shell...
, or Zebu, EP) including design bringup, build flow, debug, performance, and throughput tuning. - Experience with Verilog, VHDL... design Knowledge - Experience with C/C++, DPI, and System Verilog add-on. - Experience writing scripts using any languages...
based on algorithm requirements Implement RTL (Verilog/VHDL/SystemVerilog) for blocks like ORAN, ORAN IP compression... as required Required Skills & Experience: Strong RTL design skills in VHDL with knowledge of digital signal processing fundamentals Familiarity...
System Verilog and verify functionality using a Constrained Random Approach Use the Unified Power Format (UPF) to verify the.... You have sound knowledge of firmware and RTL design (VHDL) - experience with Cadence verification software...
, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog... and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing...
(Verilog/VHDL). Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly... and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.). C/C...
FPGA Applications Staff Engineer
technical challenges into actionable solutions. Leveraging your hands-on expertise in Verilog, SystemVerilog, or VHDL... design experience. Proven hands-on expertise in Verilog, SystemVerilog, and/or VHDL for logic design and implementation...
Synopsys ⚡ ⚡ Fri, 30 Jan 2026 02:30:41 GMT