Senior Memory Systems Design Engineer
, UltraScale+, Versal architectures) Develop and maintain RTL code using VHDL/Verilog for high-speed digital signal processing... Vivado Design Suite and associated tools IP Integrator and block design methodologies Strong RTL design skills with VHDL...
FPGA Design Technical Leader- Ethernet,PCIe, System Verilog, Xilinx- 12+ Years
in HDL languages (Verilog, VHDL and System Verilog) Hands on experience with FPGA vendor tools like Vivado, Quartus...
Cisco Systems ⚡ ⚡ Wed, 01 Jul 2026 22:27:20 GMT