is a desirable but not must.Must have been a part of one or more ASIC/SoC tape outs.Knowledge of VHDL/VERILOG.SPECMAN knowledge... of Experience in Digital RTL verification using System Verilog and UVM.Sound knowledge of constrained random verification, UVM...
is a desirable but not must.Must have been a part of one or more ASIC/SoC tape outs.Knowledge of VHDL/VERILOG.SPECMAN knowledge... of Experience in Digital RTL verification using System Verilog and UVM.Sound knowledge of constrained random verification, UVM...
description languages (HDL) like VHDL or Verilog. Strong analytical, problem-solving, and communication skills. Experience with DDR..., SystemVerilog, VHDL). Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol...
Advanced Micro Devices ⚡⚡ Sun, 08 Feb 2026 08:59:29 GMT
in ASIC or related fields Proficiency in Verilog, VHDL, and design tools like Synopsys or Cadence Strong analytical... What you need to bring: Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass...
Hewlett Packard Enterprise ⚡⚡ Sun, 08 Feb 2026 03:14:38 GMT
especially using System Verilog Have knowledge of firmware and RTL design (VHDL/Verilog) Ideally have knowledge of Cadence... Verification Methodology (UVM) draw on test scenarios using System Verilog verify functionality using the Constrained Random...
advantage. Skills/Experience Must have 3 to 15 years of practical experience with details of RTL development (VHDL... and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression, collaboration...
Applications Engineering, Staff Engineer
and HDL (Verilog/VHDL). Strong understanding of ASIC design flow. Bachelor's or Master's degree in Electronics Engineering...
Synopsys ⚡ ⚡ Sun, 15 Feb 2026 00:06:07 GMT