construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology... Graphics Modelsim/Questasim for simulation debug and reporting is required. Ability to analyze Verilog RTL to diagnose test...
SEAKR Engineering ⚡ $130000 - 165000 per year ⚡ Sat, 14 Feb 2026 23:40:17 GMT
(MBSE) Familiarity with VHDL (preferred) or Verilog, Familiarity with Vivado, Quartis, ModelSim/Questa, Aldec, ActiveHDL... and analysis, utilizing the VHDL language Average to Advanced experience with Microsoft Office Applications (Word, Excel...
Sierra Nevada Corporation ⚡ $143487.14 - 197294.81 per year ⚡ Sat, 14 Feb 2026 23:32:46 GMT
on block-level or chip-level design verification for ASICs. Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g...-silicon validation efforts Knowledge of signal processing and Verilog Assertions Ability to create, evaluate, debug...
in SysML and AADL. Knowledge of hardware engineering languages and platforms such as VHDL, Chisel, Bluespec, SystemVerilog..., and Verilog. Security and Citizenship Requirement Active and transferable U.S. government issued security clearance...
Senior Software Engineer
experience with one or more modern systems language(s): Python, Java, VHDL, Verilog, Go, Rust, etc. Versed in multithreaded...
Epirus ⚡ $171000 - 194000 per year ⚡ Tue, 17 Feb 2026 03:20:12 GMT