(requirements, design, implementation, and test). Must be knowledgeable in VHDL and/or Verilog RTL coding and be proficient in micro... Proficiency in HDL (VHDL/Verilog) Proficiency in scripting languages such as Tcl, Python, or Perl Effective communication...
(requirements, design, implementation, and test). Must be knowledgeable in VHDL and/or Verilog RTL coding and be proficient in micro... Proficiency in HDL (VHDL/Verilog) Proficiency in scripting languages such as Tcl, Python, or Perl Effective communication...
function implementation in FPGAs. Solid electronic circuit design and electronic systems background. Expertise in VHDL.../Verilog and System Verilog. Experience with FPGA design tools including AMD Vivado/Vitis and Siemens Modelsim/Questasim...
function implementation in FPGAs. Solid electronic circuit design and electronic systems background. Expertise in VHDL.../Verilog and System Verilog. Experience with FPGA design tools including AMD Vivado/Vitis and Siemens Modelsim/Questasim...
function implementation in FPGAs. Solid electronic circuit design and electronic systems background. Expertise in VHDL.../Verilog and System Verilog. Experience with FPGA design tools including Xilinx Vivado/Vitis and Mentor Modelsim/Questasim...
and architectural trade studies. Strong programming experience in one or more of: C/C++, Python, CUDA, OpenCL, SYCL, or HDL (Verilog.../VHDL). Proven ability to translate abstract architectural ideas into prototypes, benchmarks, or validated concepts...
in verification and automation. Knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C... best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration...
CesiumAstro ⚡ $113000 - 136000 per year ⚡ Sat, 06 Jun 2026 06:31:11 GMT
in verification and automation. Knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C... best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration...
in verification and automation. Knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C... best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration...
CesiumAstro ⚡ $118000 - 142000 per year ⚡ Sat, 06 Jun 2026 06:19:59 GMT
Senior Design Verification Engineer
schedule and task tracking (Agile Jira based). Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog...
Viasat ⚡ ⚡ Thu, 11 Jun 2026 03:46:00 GMT