Senior FPGA & Firmware Engineer - SDR
VHDL/Verilog where custom or performance-critical logic is required Implement designs in Vivado through the full flow... closure, and hardware bring-up Highly proficient in RTL design with VHDL and/or Verilog/SystemVerilog, including...
Lead ASIC Design Engineer
field Experience in one or more RTL languages, including VHDL, Verilog, and/or SystemVerilog Experience leading RTL design...
Mitre ⚡ ⚡ Wed, 02 Sep 2026 05:03:02 GMT