Verilog, SystemVerilog, or VHDL RTL for block-level designs including state machines, pipelines, FIFOs, and memory controllers..., implementation, and debug Strong proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines...
Experience with ASIC/FPGA design or verification Experience with Register Transfer Language - e.g. Verilog, VHDL, SystemVerilog... languages: System Verilog, System Verilog Assertions Ability to executable test plans Proficiency with Object Oriented...
Boeing ⚡ $98600 - 133400 per year ⚡ Thu, 08 Oct 2026 23:12:34 GMT
: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic. Verification... design (Verilog), simulators debuggers *Hands on Experience in Synthesis, SDC creation and support PD and STA teams...
Cadence Design Systems ⚡⚡ Thu, 08 Oct 2026 03:35:29 GMT
Responsibilities: Architect, implement, and maintain complex FPGA designs. In depth knowledge and use of VHDL, Verilog, and System... knowledge of computer hardware. Proficiency in VHDL, Verilog and System Verilog HDL languages. Strong analytical thinking...
internship/co-op session Experience with VHDL or Verilog programming Experience with FPGAs, microprocessors... (Intel), and Microchip Implement designs using VHDL for the following applications: gigabit serial interfaces, Radio...
Raytheon Technologies ⚡ $37000 - 82000 per year ⚡ Wed, 07 Oct 2026 23:18:24 GMT
SOC Engineering, Senior Engineer
Verilog, SystemVerilog, or VHDL RTL for block-level designs including state machines, pipelines, FIFOs, and memory controllers..., implementation, and debug Strong proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines...
Synopsys ⚡ ⚡ Fri, 09 Oct 2026 04:34:47 GMT