including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP... Verilog DPI-C integration with existing MATLAB and Python numerical models. Lead the development of reusable custom VIP...
CesiumAstro ⚡ $118000 - 142000 per year ⚡ Tue, 01 Sep 2026 05:35:02 GMT
solutions using VHDL, Verilog, and SystemVerilog for FPGA IP blocks and subsystem-level functionality. Develop, enhance... engineering experience. Strong understanding of RTL design principles and FPGA development methodologies. Proficiency with VHDL...
Dolby ⚡ $137100 - 188300 per year ⚡ Sun, 30 Aug 2026 05:10:41 GMT
knowledge and use of VHDL, Verilog, and System Verilog HDL languages. Experience and know how to use Matlab and other similar.... Extensive knowledge of computer hardware. Proficiency in VHDL, Verilog and System Verilog HDL languages. Strong analytical...
Proficient in VHDL (preferred) or Verilog HDL coding Familiarity with Xilinx Vivado/ISE or Altera Quartus Digital simulation... with Matlab/Simulink Experience creating unique designs and supporting legacy designs Experience with UVM/System Verilog...
synthesis (Vitis HLS) and RTL code (VHDL/Verilog/SystemVerilog). Writing, simulating, and verifying RTL and HLS implementations... \- Experience with AMD RFSoC and Versal families \- Proficiency in VHDL, Verilog, or SystemVerilog \- Experience with Vivado HLS...
FPGA Verification Engineer II
including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP... Verilog DPI-C integration with existing MATLAB and Python numerical models. Lead the development of reusable custom VIP...
CesiumAstro ⚡ $118000 - 142000 per year ⚡ Tue, 01 Sep 2026 05:35:02 GMT