Senior FPGA Engineer (Onsite)
and minimum 3 years of experience. Experience in RTL coding and simulation in Verilog or VHDL. Experience in digital circuit... verification of RTL blocks using System Verilog. Proficient using ASIC and/or FPGA simulation and synthesis tools (e.g., ModelSim...
Research Engineer
in SysML and AADL. Knowledge of hardware engineering languages and platforms such as VHDL, Chisel, Bluespec, SystemVerilog..., and Verilog. Security and Citizenship Requirement Active and transferable U.S. government issued security clearance...
Galois, Inc. ⚡ ⚡ Fri, 13 Feb 2026 23:35:39 GMT