FPGA IP Design and Verification Engineer
languages (VHDL, Verilog, SystemVerilog). Experience or knowledge in scripting languages such as Tcl, Perl, or Python. Prior...: FPGA IP Design & Validation using Verilog. Support the FPGA post-silicon system validation group in ongoing and upcoming...
Design Verification Engineer
description languages like Verilog or VHDL. Experience with simulation and debugging tools such as Synopsys VCS, Cadence Xcelium, or Questa...
Erbity Private Limited ⚡ ⚡ Tue, 14 Apr 2026 22:36:03 GMT