Senior Staff Foundation IP Engineer (Arithmetic/DSP)
for integration into FPGA fabric. Develop RTL (VHDL/Verilog/SystemVerilog) for DSP hard macros and programmable DSP slices.... 8 or more years of experience in IP design or ASIC/FPGA engineering. Strong proficiency in RTL design using Verilog...
RTL
(Must Have) Expertise in RTL design Verilog VHDL SystemVerilog RTL Micro Architecture Digital Design RTL delivery SpyGlass CDC.... Expertise in RTL design using Verilog, VHDL, and SystemVerilog. Experience with Mixed-Signal IP design, such as filter design...
Varite ⚡ ⚡ Wed, 19 Aug 2026 01:31:00 GMT