Senior RTL Design Engineer
Design Engineers design and develop digital hardware blocks using HDLs such as Verilog/SystemVerilog/VHDL for ASIC or FPGA... FPGA prototyping and silicon bring-up Skill Requirements Verilog/SystemVerilog/VHDL Digital design fundamentals...
Senior Technical Architect - SoC, Verilog, UVM, C, C++
initiatives by architecting complex solutions with Verilog, VHDL, and SystemVerilog, ensuring alignment with enterprise goals...: Enterprise Strategy and Visionary Leadership in Verilog, VHDL, SystemVerilog. 2. Solid expertise in RTL synthesis, simulation...
HCLTech ⚡ ⚡ Thu, 14 May 2026 07:57:35 GMT