, Verilog and/or VHDL) design or verification 4+ years of experience in Software programming or scripting (e.g. C/C...++ and/or Python) Preferred Qualifications: 6+ year of experience with IP Integration, RTL Design, SystemVerilog, Verilog...
Altera ⚡ $98900 - 143000 per year ⚡ Tue, 31 Mar 2026 02:33:16 GMT
FPGA Development Tools Engineer
and workflows Experience with Verilog and/or VHDL Job Type: Regular Shift: Shift 1 (Canada) Primary Location: Toronto...
Altera ⚡ ⚡ Fri, 17 Apr 2026 02:20:08 GMT