+ months of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification. 3+ months...
Altera ⚡ $90000 - 95000 per year ⚡ Thu, 05 Mar 2026 06:14:21 GMT
for test automation, data analysis, scripting, or rapid prototyping. Familiarity with FPGA development (VHDL or Verilog...
PheedLoop ⚡ ⚡ Sun, 01 Mar 2026 08:25:48 GMT
with Verilog, SystemVerilog or VHDL. Experience developing EDA/CAD optimization algorithms for FPGAs or ASICs. Experience...
Altera ⚡ $100000 - 115000 per year ⚡ Thu, 26 Feb 2026 03:01:35 GMT
in compilers. Preferred Qualifications Contributions to MLIR or Clang open-source projects. Experience with Verilog/VHDL...
Altera ⚡ ⚡ Thu, 26 Feb 2026 02:29:55 GMT
FPGA IP Design Engineer Intern
+ months of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification. 3+ months...
Altera ⚡ $90000 - 95000 per year ⚡ Thu, 05 Mar 2026 06:14:21 GMT