Design Engineering Architect
: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic. Verification... design (Verilog), simulators debuggers *Hands on Experience in Synthesis, SDC creation and support PD and STA teams...
Senior Applications Engineer - Emulation
: Experience with an Emulation platform (Veloce, Palladium, Zebu) is preferred SystemVerilog, Verilog and/or VHDL RTL design...
Siemens ⚡ ⚡ Wed, 29 Apr 2026 01:40:21 GMT