of technical solutions. VHDL/Verilog simulation (pre-synthesis & post-layout verification). Design synthesis and implementation...: VHDL, Verilog and System Verilog Simulation with ModelSim/Questa Core Synthesis with Synplify/Vivado Implementation...

of technical solutions. VHDL/Verilog simulation (pre-synthesis & post-layout verification). Design synthesis and implementation...: VHDL, Verilog and System Verilog Simulation with ModelSim/Questa Core Synthesis with Synplify/Vivado Implementation...

Strong experience in FPGA design and development Proficiency with VHDL and/or Verilog Experience with FPGA verification...

, with participation in current and future developments. Functions: Coding in VHDL/Verilog. Verification by testbenches Code coverage... with background and interest in VHDL/Verilog, FPGA development tools (Vivado, ModelSIM), synthesis and implementation, scripting...

of DSP algorithms and their implementation in RTL (Verilog/VHDL) or high-level languages (C/C++). Support the evolution... of our custom space-tailored radio platforms. Main languages/technologies used: Verilog/SystemVerilog. Yosys/Xilinx Vivado...

Verilog or VHDL based on architecture specifications Apply timing constraints and support timing closure activities... skills using Verilog or VHDL Experience with timing constraints and timing analysis Understanding of block level testing...

and AMBA CHI based cores Work with AXI, CHI or AHB protocols where required Develop RTL using Verilog or VHDL Support block... Proficiency in RTL design using Verilog or VHDL Experience with block level testing Strong analytical and problem solving skills...

with Ethernet SERDES PHY and controller integration Strong Verilog experience Proficiency in RTL design using Verilog or VHDL... related blocks Work on Ethernet SERDES PHY and controller integration Translate architecture requirements into Verilog...

with Xilinx or Altera FPGAs Hands on experience with Vivado or Quartus Knowledge of Verilog, SystemVerilog or VHDL Experience...

and review RTL using Verilog or VHDL Apply timing constraints and support timing closure activities Perform block level... RTL design experience using Verilog or VHDL Experience with timing constraints and timing analysis Understanding...

and evolve the target architecture for ASIC. Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog). Analyze and optimize...

Pitaya, or defense-grade SDR hardware. · Knowledge of GNU Radio, MATLAB/Simulink, Python, C/C++, VHDL/Verilog, or embedded...

. Nice-to-have training / specific knowledge: · Experience with frontend RTL design using VHDL, Verilog, or SystemVerilog...

. Knowledge of networking concepts (Gateways, port forwarding, etc.). Knowledge of VHDL/Verilog. Familiarity with MPLAB Harmony...

de VHDL y/o Verilog-SystemVerilog. Conocimiento de los estándares de aviación (DO-254) y de la agencia espacial europea...

hacerlo repetible, documentable y transferible. Se valorará · Experiencia con FPGA o HDL: VHDL, Verilog, SystemVerilog...

de vida: requisitos, documentación, diseño, implementación, validación y verificación. Diseño e implementación en VHDL... en VHDL. Uso de herramientas como Vivado, Vitis, QuestaSim, entre otras. Pruebas con instrumentación electrónica...

hacerlo repetible, documentable y transferible. Se valorará · Experiencia con FPGA o HDL: VHDL, Verilog, SystemVerilog...

en el área de redes (Gateways, port forwarding, etc.). - Conocimientos en VHDL/Verilog. - Familiaridad con MPLAB Harmony...

y la diversidad. Xilinx, MPSoC, FPGA, ASIC, RTL, VHDL, Verilog,... principales tareas serían: - Definir y evolucionar la arquitectura objetivo para ASIC. - Desarrollar y adaptar bloques RTL (VHDL...