Lead Software Engineer - Logic Synthesis
VHDL/Verilog feature support in synthesizer. Logic optimization and performance improvement in synthesizer. Position... should be proficient with C/C++, Operating system concepts. Design modeling using Verilog/SV, VHDL or SysC. Knowledge and experience...
Lead Software Engineer - Liberate
simulation is important. Knowledge of Verilog and VHDL is also highly desirable. Have a good understanding of library...
Cadence Design Systems ⚡ ⚡ Thu, 23 Jul 2026 03:39:18 GMT