APAC Algo Trading Low Latency C++ Developer
. Design and implement real-time trading rules and risk checks using FPGA (Verilog/VHDL) or C++. Architect cycle-accurate FPGA... (Verilog/VHDL) or low-latency C++ development. Expert in C++17/20/23, Linux system programming, concurrency. Deep knowledge...
Field Applications Engineer
(Verilog/VHDL) Good understanding of SoC architectures and methodologies Proficiency with core EDA tools, methodologies...
Siemens ⚡ ⚡ Tue, 15 Sep 2026 23:58:08 GMT