Lead Software Engineer (Synthesis software)
will be implementing new VHDL/Verilog construct & feature support in synthesizer. He will be working on logic optimization.... 3. Design modeling using Verilog/SV, VHDL or SysC. 4. Knowledge and experience in RTL modeling of BFMs...
Application Engineer
etc. Experience with VHDL, Verilog and FPGA verification tools. Hands-on experience with high density FPGA design or ASIC design...
Altera ⚡ ⚡ Wed, 29 Apr 2026 02:41:58 GMT