SC Cleated FPGA Engineer
communications interfaces using VHDL or Verilog/SystemVerilog in AMD/Xilinx Vivado Lead SoC hardware/software co-design... workflows (e.g., ModelSim, Questa or Vivado Simulator) Solid HDL capability across VHDL, Verilog and/or SystemVerilog...
Security Researcher
such as VHDL or Verilog. Fundamental understanding of digital and wireless communications, cellular architectures, mobile network...
Ericsson ⚡ ⚡ Fri, 07 Aug 2026 22:33:07 GMT