/improvement. Job Requirements: 4-6 or above years’ experience in the following areas: 1. Design experience in Verilog/VHDL... for IP or SoC chip level. 2. Verification with knowledge of System Verilog/VHDL and HDL simulators. 3. Experience...
Cadence Design Systems ⚡⚡ Sat, 13 Jun 2026 01:05:13 GMT
Lead Application Engineer - Design Verification
/improvement. Job Requirements: 4-6 or above years’ experience in the following areas: 1. Design experience in Verilog/VHDL... for IP or SoC chip level. 2. Verification with knowledge of System Verilog/VHDL and HDL simulators. 3. Experience...
Cadence Design Systems ⚡ ⚡ Sat, 13 Jun 2026 01:05:13 GMT