Ams verification engineer
collaboration skills and a proactive attitude.experience with system verilog real-number modelling is highly valued.familiarity... with mixed-signal simulation platforms such as mentor questa, adms, cadence xcelium ams, synopsys vcs ams.knowledge of vhdl...
Junior Digital Design and RISC-V Architectures Engineer
). Fundamental knowledge of hardware description languages (HDL) such as Verilog or VHDL, and digital design tools for synthesis...
Fondazione Chips-IT ⚡ ⚡ Sat, 15 Aug 2026 22:11:17 GMT