Sr. Staff Verification Engineer
Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities... Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL Experience with consumer and/or ITA market circuit...
Staff Verification Design Engineer
Hands-on experience with System Verilog as High-level Verification Language and UVM implementation. Debugging digital... Desired Qualifications Experience of setting up UVM verification environment from scratch Familiarity with VHDL or System...
Sierra Wireless ⚡ ⚡ Sat, 16 May 2026 03:04:45 GMT