QA Test Engineer
Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF, and UVM. Key Responsibilities: Master the QuestaSim Simulator and develop.... Strong knowledge of Hardware Description Languages (Verilog, VHDL, or SystemVerilog) is required. Knowledge of UVM...
Field Application Engineer
and HDL languages (SystemVerilog, Verilog, and VHDL). Scripting experience with Python, Shell, and/or Perl...
Siemens ⚡ ⚡ Sat, 27 Jun 2026 07:55:32 GMT