ASIC Digital Design, Principal Engineer
, with significant work in high-speed or mixed-signal environments Strong proficiency in Verilog or VHDL for RTL design and gate-level... that everyone else missed. You think in terms of design intent, not just passing checks. When you write Verilog, you are already thinking...
Staff Application Engineer
Veloce, or Cadence Palladium Strong working knowledge of Verilog, SystemVerilog, or VHDL and verification methodologies...
Synopsys ⚡ $106000 - 160000 per year ⚡ Sat, 17 Oct 2026 22:57:14 GMT