You are: Minimum 5 years of experience designing using RTL/Verilog/VHDL on FPGAs. Experience with video systems and specification... with Verilog, SystemVerilog, VHDL, Xilinx Vivado, Altera Quartus, and/or ModelSim RTL design and verification including test...
Fidus Systems ⚡ $125000 - 160000 per year ⚡ Thu, 23 Jul 2026 22:37:04 GMT
You are: Minimum 5 years of experience designing using RTL/Verilog/VHDL on FPGAs. Experience with video systems and specification... with Verilog, SystemVerilog, VHDL, Xilinx Vivado, Altera Quartus, and/or ModelSim RTL design and verification including test...
Fidus Systems ⚡ $125000 - 160000 per year ⚡ Thu, 23 Jul 2026 22:25:59 GMT
coding VHDL, Verilog and SystemVerilog Experience in SystemVerilog+UVM Experience with FPGA compilation tools Experience... and document the design using Verilog, SystemVerilog Develop and document the verification environment using SystemVerilog + UVM...
Qualcomm ⚡ $90100 - 135100 per year ⚡ Wed, 22 Jul 2026 07:43:59 GMT
coding VHDL, Verilog and SystemVerilog Experience in SystemVerilog+UVM Experience with FPGA compilation tools Experience... and document the design using Verilog, SystemVerilog Develop and document the verification environment using SystemVerilog + UVM...
Qualcomm ⚡ $90100 - 135100 per year ⚡ Wed, 22 Jul 2026 02:10:07 GMT
. Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL. Understanding of ASIC/VLSI... in Verilog RTL Analyze performance, area, power, and system cost tradeoffs for different implementations Review...
Qualcomm ⚡ $104900 - 154900 per year ⚡ Sat, 18 Jul 2026 03:48:18 GMT
, implementation or related work experience Expert Verilog/VHDL RTL design languages and ability to write clean, readable... (UVM), and/or SystemC, Expert hardware description languages (HDL): Verilog and/or SystemVerilog Good working experience...
Qualcomm ⚡ $124200 - 174200 per year ⚡ Fri, 17 Jul 2026 01:08:24 GMT
in SystemVerilog or Verilog V2K/VHDL Architect and develop models to verify system architecture. Provide oversight and direction... Standard Protocol knowledge – Ethernet, ESUN, UALink, OTN Solid experience with VHDL, Verilog and SystemVerilog Experience...
FPGA Digital Design Engineering Intern (January 2027) (4-16 months)
in an Electrical or Computer Engineering degree program, or equivalent; Experience with Verilog, SystemVerilog, or VHDL...
Kepler Communications ⚡ $29.75 - 39 per hour ⚡ Fri, 24 Jul 2026 01:59:32 GMT