proposals to the client Who You are: Minimum 5 years of experience designing using RTL/Verilog/VHDL on FPGAs. Experience... understanding of tool flow Experience with Verilog, SystemVerilog, VHDL, Xilinx Vivado, Altera Quartus, and/or ModelSim RTL design...
Fidus Systems ⚡ $125000 - 160000 per year ⚡ Thu, 22 Oct 2026 22:43:19 GMT
DSP - FEC Design Engineer
and languages such as Verilog or VHDL is a plus. Team player with a mindset focused on the successful delivery of the first product...
Celero Communications, Inc. ⚡ ⚡ Thu, 29 Oct 2026 07:32:00 GMT