, or related field. 0-2 years of ASIC hardware design and/or implementation experience. Verilog/VHDL RTL design languages... modules and sub-systems and integrate IP from other teams in Verilog RTL Analyze performance, area, power, and system cost...
Qualcomm ⚡ $90100 - 135100 per year ⚡ Sat, 07 Feb 2026 07:05:25 GMT
, Verilog, VHDL, UVM, and scripting/programming in C/C++. You're proactive, inclusive, and passionate about process improvement... with at least 12+ years of direct industry experience in digital design verification with System Verilog, Verilog, or VHDL. Expertise...
; 8+ years of digital verification experience. Expertise in System Verilog, Verilog, or VHDL and UVM. Experience.... You're skilled in System Verilog, UVM, scripting, and bring a creative, systematic approach to problem-solving...
in Verilog or VHDL. Your approach is rooted in both theoretical knowledge and practical experience, allowing you to bridge the... proficiency in Verilog or VHDL for ASIC development. Experience with code quality metrics and coverage-driven verification...
/AEH) Proficiency with Vivado (synthesis, implementation, timing closure, and debug) Solid RTL development skills (VHDL... and/or Verilog/SystemVerilog) Hands-on experience with video processing pipelines and 4K resolution Certification standards (DO-254...
challenges that push the boundaries of what's possible in high-speed chip development. Your foundation in Verilog or VHDL is rock... Be Doing: Designing and verifying complex ASIC digital and mixed-signal systems using Verilog or VHDL. Analyzing digital...
experience Expert Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL. Deep understanding... hardware description languages (HDL): Verilog and/or SystemVerilog Good working experience with C (basic level or C...
, test plans, VHDL/Verilog coding right through to simulation. You will be responsible for FPGA functional allocation, logic... design flow, including RTL design with SystemVerilog/Verilog/VHDL, simulation, logic synthesis and timing closure...
Curtiss-Wright ⚡ $74600 - 124400 per year ⚡ Sat, 13 Dec 2025 02:46:33 GMT
ASIC Design Engineer, Low Power Audio AI Subsystems
, or related field. 0-2 years of ASIC hardware design and/or implementation experience. Verilog/VHDL RTL design languages... modules and sub-systems and integrate IP from other teams in Verilog RTL Analyze performance, area, power, and system cost...
Qualcomm ⚡ $90100 - 135100 per year ⚡ Sat, 07 Feb 2026 07:05:25 GMT