FPGA Design - Lead Research Engineer
understanding of digital logic design, including FSMs, pipelining, and resource optimization. 2-5 years of experience with RTL...Job Description Summary As an FPGA Design Research Engineer, you will have the opportunity to architect and develop...
FPGA Design - Lead Research Engineer "CLEARANCE REQUIRED"
understanding of digital logic design, including FSMs, pipelining, and resource optimization. 2-5 years of experience with RTL...Job Description Summary As an FPGA Design Research Engineer, you will have the opportunity to architect and develop...
GE Vernova ⚡ $98400 - 164000 per year ⚡ Sun, 14 Jun 2026 07:46:08 GMT