ASIC or RTL Design Engineer
behavioral SystemVerilog models of analog blocks Validating models against transistor-level simulation results Debugging... in debugging failures in simulation and waveforms. Familiarity with high-speed interface standards is a plus....
Junior Data Scientist
design. Debugging & Problem-Solving: Strong troubleshooting abilities to distinguish between model and code issues. Agile...
SFE ⚡ $85000 - 95000 per year ⚡ Tue, 03 Nov 2026 23:40:39 GMT