ASIC/RTL Design Engineer 5
behavioral SystemVerilog models of analog blocks Validating models against transistor-level simulation results Debugging... debugging failures in simulation and waveforms. Familiarity with high-speed interface standards is a plus. Comments...
Firmware Engineer
error management. #4. Hands-on experience with JTAG/ICE debugging and firmware debugging, validation, and root-cause.... Enhance DRAM/SRAM usage efficiency and reduce Write Amplification for better endurance and performance. Debugging...
VeeRteq Solutions Inc. ⚡ $180000 per year ⚡ Tue, 03 Nov 2026 23:52:20 GMT