in hardware design and/or verification methodologies. Solid hands‑on verification experience using UVM, SystemVerilog, Verilog..., VHDL, SystemC, and SystemVerilog Assertions (SVA). Hands‑on experience with Cadence Verification IP or Jasper...

in hardware design and/or verification methodologies. Solid hands‑on verification experience using UVM, SystemVerilog, Verilog..., VHDL, SystemC, and SystemVerilog Assertions (SVA). Hands‑on experience with Cadence Verification IP or Jasper...

Engineering, or a related field (or equivalent experience). Strong FPGA development experience using Verilog, SystemVerilog..., and/or VHDL. Hands-on experience with industry-standard tools such as Xilinx Vivado or Synplify. Proven experience...