Design & Verification Engineer Leader- Semiconductor (LSI)
as follows; *Front-end design and verification of ASIC *RTL design by Verilog HDL/VHDL *Design and verification using a general... specifications (English) RTL (Verilog / SystemVerilog) Verification strategy (English) Verification item table (English) Verification...
Sr Principal Application Engineer
with Verilog/VHDL/SystemVerilog UVM is a must. - Knowledge and experiences on emulator/accelerators (Palladium, Zebu, Veloce...
Cadence Design Systems ⚡ ⚡ Sun, 18 Jan 2026 08:35:21 GMT