, Verilog and/or VHDL) design or verification 4+ years of experience in Software programming or scripting (e.g. C/C...++ and/or Python) Preferred Qualifications: 6+ year of experience with IP Integration, RTL Design, SystemVerilog, Verilog...
Altera ⚡ $98900 - 143000 per year ⚡ Tue, 31 Mar 2026 05:21:03 GMT
Senior Embedded Software Designer
Experience with RTL (Verilog and/or VHDL) and embedded SoCs Salary Range: $159,288 - $209,288 CAD Actual total compensation...
Kepler Communications ⚡ ⚡ Tue, 12 May 2026 01:52:07 GMT