and layout guidelines. Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data... synthesizable RTL in SystemVerilog, Verilog, or VHDL. Hands-on experience with FPGA design suites and EDA tools (e.g., AMD/Xilinx...
and layout guidelines. Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data... synthesizable RTL in SystemVerilog, Verilog, or VHDL. Hands-on experience with FPGA design suites and EDA tools (e.g., AMD/Xilinx...
and layout guidelines. Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data.... Proficiency in writing synthesizable RTL in SystemVerilog, Verilog, or VHDL. Hands-on experience with FPGA design suites and EDA...
diagrams and layout guidelines. Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control... development. Proficiency in writing synthesizable RTL in SystemVerilog, Verilog, or VHDL. Hands-on experience with FPGA design...
, planning, and execution of firmware design and development Developing FPGA VHDL code for Microchip/Xilinx (AMD)/Altera (Intel... experience in Digital Electrical Engineering. 9+ plus years of firmware development experience Working experience using VHDL...
L3Harris Technologies ⚡⚡ Wed, 05 Aug 2026 05:56:25 GMT
to architecture, design, and implementation of FPGA based digital systems Develop RTL in Verilog, SystemVerilog, or VHDL for control... or a related field 2+ years FPGA design experience, including Xilinx Vivado Strong knowledge of System Verilog and/or VHDL...
Viasat ⚡ $104500 - 164500 per year ⚡ Mon, 13 Jul 2026 04:17:42 GMT
in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions Integrate and deploy designs... Xilinx Vivado Strong knowledge of System Verilog and/or VHDL Experience with RTL design for various signal processing...
Viasat ⚡ $104500 - 164500 per year ⚡ Sun, 12 Jul 2026 07:51:36 GMT
Senior Design Verification Engineer (Space)
tracking (Agile Jira based) Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code...
Viasat ⚡ ⚡ Fri, 25 Sep 2026 07:32:17 GMT