, and static timing analysis. Expertise with Verilog and a scripting language such as Python, TCL, or PERL. Experience... with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred. Familiarity with SystemVerilog, UVM, VHDL, C...
Teradyne ⚡ ⚡ Thu, 20 Aug 2026 04:55:52 GMT
Knowledge in Hardware Description Language such as Verilog or VHDL an advantage Knowledge in programming languages (ie. Python...
Lattice Semiconductor ⚡ ⚡ Tue, 18 Aug 2026 05:40:29 GMT
using Verilog/SystemVerilog/VHDL o Synthesis and timing analysis o Place and route o Advanced IC packaging o DFT...
Siemens ⚡ $35.48 - 63.84 per hour ⚡ Tue, 11 Aug 2026 22:51:17 GMT
Semiconductor Design Engineer (Compute Test, Oregon)
, and static timing analysis. Expertise with Verilog and a scripting language such as Python, TCL, or PERL. Experience... with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred. Familiarity with SystemVerilog, UVM, VHDL, C...
Teradyne ⚡ ⚡ Thu, 20 Aug 2026 04:55:52 GMT