good knowledge in VHDL. Verilog, System Verilog is a plus. Very good understanding of physical and timing constraints..., you will be responsible to define, implement and verify designs implemented in RTL VHDL in any of our working fields: Launchers (Ariane 6...
FPGA Development Engineer
good knowledge in VHDL. Verilog, System Verilog is a plus. Very good understanding of physical and timing constraints..., you will be responsible to define, implement and verify designs implemented in RTL VHDL in any of our working fields: Launchers (Ariane 6...
Airbus ⚡ ⚡ Wed, 11 Feb 2026 23:53:53 GMT