项目在各阶段的顺利推进 任职要求: 微电子、电子工程、计算机工程或相关专业硕士学历 有高速接口、复杂数字系统IP 设计项目经验者优先 具备扎实的数字电路基础,理解 ASIC 设计和验证的完整流程 熟悉硬件描述语言Verilog/VHDL,熟悉Perl... description languages such as Verilog and/or VHDL, Experience with scripting languages such as Perl, Tcl, C Shell, Python, and/or Makefile...
Cadence Design Systems ⚡⚡ Sat, 10 Jan 2026 08:22:05 GMT
Design Engineer II
项目在各阶段的顺利推进 任职要求: 微电子、电子工程、计算机工程或相关专业硕士学历 有高速接口、复杂数字系统IP 设计项目经验者优先 具备扎实的数字电路基础,理解 ASIC 设计和验证的完整流程 熟悉硬件描述语言Verilog/VHDL,熟悉Perl... description languages such as Verilog and/or VHDL, Experience with scripting languages such as Perl, Tcl, C Shell, Python, and/or Makefile...
Cadence Design Systems ⚡ ⚡ Sat, 10 Jan 2026 08:22:05 GMT