Research Assistant (RTH)
/VHDL, System Verilog, Python, C/C++, Matlab; R&D experiences of using Cadence and Synopsys EDA tools or machine learning... design, FPGA prototyping, AI algorithm design; Strong programming skills of at least one of the following languages: Verilog...
Research Assistant (RTH)
/VHDL, System Verilog, Python, C/C++, Matlab; R&D experiences of using Cadence and Synopsys EDA tools or machine learning... design, FPGA prototyping, AI algorithm design; Strong programming skills of at least one of the following languages: Verilog...
⚡ ⚡ Mon, 02 Feb 2026 23:52:49 GMT