Research Assistant (RTH)
/VHDL, System Verilog, Python, C/C++, Matlab; R&D experiences of using Cadence and Synopsys EDA tools or machine learning... design, FPGA prototyping, AI algorithm design; Strong programming skills of at least one of the following languages: Verilog...
Lead/ Senior/ Research Engineer
programming skills of at least one of the following languages: Verilog/VHDL, Verilog-A, System Verilog, Python, C/C++, and HLS; R...
Leadingnation ⚡ ⚡ Sat, 18 Jul 2026 22:18:42 GMT