of digital design fundamentals, RTL (Verilog/VHDL), and synthesis concepts. Experience with constrained-random, coverage-driven..., and top-level (full-chip) verification, including analog/digital interaction using Verilog-AMS / real-number modeling. Debug...
Allegro MicroSystems ⚡⚡ Sun, 04 Oct 2026 00:31:37 GMT
Senior Digital Verification Engineer
of digital design fundamentals, RTL (Verilog/VHDL), and synthesis concepts. Experience with constrained-random, coverage-driven..., and top-level (full-chip) verification, including analog/digital interaction using Verilog-AMS / real-number modeling. Debug...
Allegro MicroSystems ⚡ ⚡ Sun, 04 Oct 2026 00:31:37 GMT