development would be advantageous. Experience with VHDL, Verilog, and Git will be beneficial. Familiarity with Windows-based...
Jenrec Recruitment ⚡ ⚡ Thu, 05 Nov 2026 23:58:28 GMT
Junior Electronic Hardware Test Engineer - Paarl
development would be advantageous. Experience with VHDL, Verilog, and Git will be beneficial. Familiarity with Windows-based...
Jenrec Recruitment ⚡ ⚡ Thu, 05 Nov 2026 23:58:28 GMT