development would be advantageous. Experience with VHDL, Verilog, and Git will be beneficial. Familiarity with Windows-based...
Jenrec Recruitment ⚡ ⚡ Sun, 06 Sep 2026 22:09:42 GMT
Junior Electronic Hardware Test Engineer - Paarl
development would be advantageous. Experience with VHDL, Verilog, and Git will be beneficial. Familiarity with Windows-based...
Jenrec Recruitment ⚡ ⚡ Sun, 06 Sep 2026 22:09:42 GMT