design entry (VHDL or Verilog). RTL simulation (Mentor, Cadence, ...). Logic Synthesis and Timing Closure (Synopsys...
Keysight Technologies ⚡ ⚡ Fri, 19 Jun 2026 06:59:27 GMT
Keysight Technologies ⚡ ⚡ Fri, 19 Jun 2026 01:13:02 GMT
background in digital communications and signal processing Hands-on experience with FPGA design (VHDL/Verilog/SystemVerilog...
IDLab UGent ⚡ ⚡ Fri, 29 May 2026 22:26:01 GMT
a plus Familiar with Cadence EDA tools, Synopsys Spyglass, VHDL/Verilog/SystemVerilog, Python Strong analytical, debugging, and hands...
microTECH Global ⚡ €60 - 73 per hour ⚡ Fri, 22 May 2026 05:05:46 GMT
(Verilog/VHDL) Experience with video, imaging, or display processing Familiarity with hardware/software co-design...
Vivid Resourcing ⚡ ⚡ Fri, 01 May 2026 23:17:53 GMT
Digital Signal Processing ASIC R&D Engineer
design entry (VHDL or Verilog). RTL simulation (Mentor, Cadence, ...). Logic Synthesis and Timing Closure (Synopsys...
Keysight Technologies ⚡ ⚡ Fri, 19 Jun 2026 06:59:27 GMT