Senior / Lead Data Converter IC Design Engineer (FinFET)
Responsibilities Architect and design multi-GS/s ADC/DAC architectures (Time-Interleaved SAR, Pipeline, Flash, or RF-DACs). Deliver... constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
Senior / Lead Data Converter IC Design Engineer (FinFET)
Responsibilities Architect and design multi-GS/s ADC/DAC architectures (Time-Interleaved SAR, Pipeline, Flash, or RF-DACs). Deliver... constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
Encore Semi ⚡ $150000 - 180000 per year ⚡ Sat, 17 Oct 2026 22:23:31 GMT