Mixed Signal Systems and Verification Engineer I
with low‑power architectures. Exposure to SystemVerilog UVM methodologies. Experience with FPGA prototyping. Familiarity... en SystemVerilog. Expérience en prototypage FPGA. Familiarité avec des normes industrielles telles que PCIe, USB, DDR ou équivalentes...
Engineer Digital 3
-Speed Digital Design and Verification Experience with FPGA/SOC/ASIC implementation (VHDL/Verilog, Synthesis, Timing Closure...
Artech Information Systems ⚡ ⚡ Thu, 23 Jul 2026 06:44:04 GMT